Please find below the description of the CAD Support Job Openings. We would look forward for more people like “U” to be a part of SmartPlay!!
If the referred candidate(s) join in two weeks time, i.e, by 15 Nov 10, HOT JOB Bonus would be awarded else Standard Bonus would be awarded
Sned your CV's to
pradeep.sakhamoori@smartplayin.com
Location: Bangalore
Position : PD CAD support
• Objective
– supporting Power integrity analysis methodology and tools in advanced technologies like 28nm.
– Static and Dynamic voltage drop tools and reference flow support
-- Work closely with design teams to establish new voltage drop, electro migration, ESD and low power related methodologies for power grid verification and sign off
- Prepare and maintain regression suites, test cases/tutorials and documents/user guides
Skill Set requirement
· Strong preference: 2-3 years of experience with using Apache- Red hawk or a similar voltage drop analysis tool
· In-depth understanding of key concepts like static voltage drop, dynamic vector less / VCD based voltage drop, average power, key components of average power (switching, internal and leakage) power gates, ramp up, low power design and ESD phenomenon
· Highly skilled in scripting languages like PERL and TCL. Knowledge of C/C++ is preferred.
· Good documentation as well as presentation skills.
· Good grasp of fundamentals of DC, transient and AC (frequency domain) analysis are strongly preferred.
· Prior experience in supporting and automating voltage drop analysis and power grid signoff for chip tape outs is strongly preferred.
· Sound understanding of static timing analysis and its key concepts like setup, hold, slack, timing closure etc
· Sound understanding of the physical design cycle including floor planning, placement, clock tree synthesis and routing, timing closure, power grid sign off and backend verification.
· Sound understanding of basic logic circuit design
Education: Bachelor’s in Electrical/Computer Engineering is compulsory. Master’s is preferred
Location: Bangalore
Position : PD CAD support
•
Objective
- Supporting Netlist to GDSII flow and tools in advanced technologies like 28nm.
- Place and route reference flow support from floor planning, placement, CTS, routing, RC extraction, BE verification and timing closure.
- Work closely with physical design implementation team and tool supplier to define flows for macro and top level flow, resolve issues, improve QoR and turn-around time. Run regressions and ensure the reference flows are stable and ready for use in products.
- Prepare and maintain regression suites, test cases/tutorials and documents/user guides
Skill Set requirement
· Strong preference: 2-3 years of experience with using place and route flows in advanced technologies.
· Hands on experience with RC extraction and timing analysis tools is an added advantage.
· Highly skilled in scripting languages like PERL and TCL. Knowledge of C/C++ is preferred.
· Good documentation as well as presentation skills.
· Sound understanding of the physical design cycle including floor planning, placement, clock tree synthesis and routing, timing closure, power grid sign off and backend verification.
· Sound understanding of basic logic circuit design
Education: Bachelor’s in Electrical/Computer Engineering is compulsory. Master’s is preferred.
Location: Bangalore
Position : PD CAD support
• Objective
– Supporting IP characterization and modeling flow and tools in advanced technologies like 28nm
– Support advanced timing, power and noise model characterization and modeling for Standard cells, Pads, memories and analog IP.
– Support creation and QA of verilog, power and timing views. Run regressions and ensure the reference flows are stable and ready for use in products.
– Prepare and maintain regression suites, test cases/tutorials and documents/user guides
Skill Set requirement
· Strong preference: 2-3 years of experience with characterization and modeling tools. Spice simulations for model QA and ability to develop flows for verification of timing/power/verilog views.
· Highly skilled in scripting languages like PERL and TCL. Knowledge of C/C++ is preferred.
· Good documentation as well as presentation skills.
· Sound understanding of basic logic circuit design
Education: Bachelor’s in Electrical/Computer Engineering is compulsory. Master’s is preferred.
4) Job Code:
Location: Bangalore
Position : FE CAD Development
•
Objective
– Work in the area of ASIC front-end design and verification automation.
– Develop in-house programs that convert design data from documents, convert such design data across different formats, generate RTL and test bench codes from the extracted design data.
Skill Set requirement
- Perl scripting, make file, C/C++ programming
- VHDL, Verilog,
- Simulation using MTI, NCsim or VCS
