Refer your friends for exciting opportunities - HCL

Every now and then someone needs that little push to spur them on to success. At HCL, we are providing  just that opportunity with our referral program. Go through the available positions, and if you know people who have the skills and aptitude to make it big here, send us their CVs. Walk-in Date & Time: 10th April 2011 (Sunday) -  10AM to 12:30PM. Work Location: Chennai | Position: Lead Engineer/ Technical Lead/ Senior Technical Lead  Qualification: BE / B. Tech / M.E/ M. Tech / MS (EEE, IT, ECE, CSE)/ M.SC (CSE / IT)/MCA   Walk in Venue The ideal candidate should possess Skills Total  experience HCL Technologies Ltd, No.8&9, G.B.Palya,  Off Hosur Road,  Bangalore - 560068 Tel.: +91-80-41584000 Land Mark : Adjacent to RNS Maruti Showroom ·         Extensive experience in C / C++ ·         Experience in System Programming (Non Application Dev Background) ·         Good Knowledge & Exp in Unix / Linux / VXworks / Solaris ·         Experience in Networking Domain is mandatory (atleast 60 - 70 % of his experience ) ·         Willingness to take role of individual contributor (Pure Technical Role) ·         We expect the candidate to be strong in any of the below area: o    Layer 2 LAN protocols like MSTP, RSTP, PVST, LACP, VRRP o    Layer 3 protocols like RIP, OSPF, BGP, Multicast routing - PIM-SM, PIM-DM, DVMRP   o    MPLS , IPV4, IPV6 o    Video, Cable, RF Gateway   o    Layer 4 – 7 protocol optimization : GRE ,AH , Diameter,DNS, DHCP,  LDAP ,RADIUS,RTP, RTSP, cmts, “cable modem”, Docsis Open Systems, C / C++ 5 – 9 years You may send the resume(s) to Padmapriyap@hcl.com We also have other requirements. Please send their resumes to the respective email ids mentioned in the document attached. Shortlisted candidates will be directly contacted for interviews. Please refer to the attached document for more details Note: For the walk-in drive, candidates must carry the documents mentioned below: 1.      Hard copy of updated resume 2.      Last three months' salary slip 3.      One (1) passport-sized photo 4.      Please mention the name and employee code of the person who has referred you on the resume Regards, Team HR

For internal circulation only : Internal Communication – HR

TCS written tests for B.Sc and Diploma graduates at Hyderabad

Dear Associate,

Greetings from Talent Acquisition Team!

It is with great pleasure that TCS announces the recruitment drive for B.Sc and Diploma graduates. Candidates successfully clearing the selection process will be deployed on world-class projects on successful completion of training (a comprehensive exercise in itself that lasts for around seven months).

These recruits will enjoy equal opportunities at par with engineers based on their individual performance.

In this regard, TCS plans to cordially invite all the eligible candidates to take part in the selection process and become a part of the TATA family. Kindly note the following eligibility criteria:
•        Candidates from the 2010 - 2011 batch are eligible to apply.
•        BSc (Mathematics / Statistics / Physics / Chemistry / Computer Science / Computer Applications / Electronics / IT / Bioinformatics), BCA, BCS, Diploma (IT / Computer Science / ECE / EEE). (For more details, please refer the 'Eligibility Criteria' in posted appended herewith)

Eligible & Interested candidates can walk-in for a written test on below dates & Venues:

Date             :        10th April, 2011
Venue         :        Osmania University, KOTIwomensCollege
Address      :        Andhra Bank,

Koti Circle

, Koti, Hyderabad 500095
Time            :        9:30 AM to 12:30 PM

Date             :        12th April 2011
Venue         :        AuroraDegreeCollege, Chikkadpally
Address      :        1-8-167/2/2/A, Street Number 8, KR Chambers, Chikkadpally, Hyderabad 500020.
Time            :        9:30 AM to 12:30 PM

Smartplay - Hiring - VLSI Engineers.- Bangalore, Noida, Malaysia, USA

Team,

SmartPlay is hiring…. More engineers like you…!

We have multiple job openings in VLSI as described below. Go ahead and please refer all your friends and buddies whom you think can fit in to the following requirements. All those who join by 18 Apr 11 would be eligible for HPT JOB Bonus and anyone who is getting onboard would be eligible for STANDARD Bonus

Kindly mail all your referrals to pradeep.sakhamoori@smartplayin.com mentioning the title of the job in the subject line.

FRESHERS PLEASE EXCUSE 

Physical Design

Experience Level          : 2-10yrs

Education              : BE / MS or ME / MTech / MS in an Electronics / Electrical Engineering

Location                       :  Bangalore, Noida, Malaysia and USA (H1)

Mandatory Skills required:

·         Implementation of multimillion gate SoC designs in cutting edge process technologies (28nm, 45nm & 65nm)

·         Work on all aspects of physical design including synthesis, floor planning, place and route, clock distribution, IP integration, extraction, timing closure, power and signal integrity analysis, physical verification, DFM, and tapeout .

·         Clear understanding and command over all aspects of physical design

·         Expertise in Synopsys IC Compiler / Magma Talus / Cadence SoC Encounter  

·         Skill and experience in scripting using Tcl or Perl desirable

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Design Verification

Experience Level          : 2 - 8yrs

Education              : BE / MS or ME / MTech / MS in an Electronics / Electrical Engineering

Location                       :  Bangalore, Noida, Malaysia and USA (H1)

Mandatory Skills required:

·         Proficiency in one or more HVL's a must (System Verilog, C++, Vera, e, System C, test builder).

·         Strong domain knowledge on one or more - PCIe, USB, Ethernet, ARM, AHB/AXI, AMBA

·         Should have worked on SOC verification on at least one project with constrained random methodology (eRM/VMM/OVM).

·         Must be expert in building a verification env with any of the above methodology, writing and debugging test cases.

·         Good in concepts Code coverage and functional coverage.

·         Expertise in Verilog and / or VHDL is desired

·         Working knowledge of any one scripting language like Perl, Python, Unix Make, Unix Shell Scripts etc

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DFT

Experience Level          : 5+ yrs

Education              : BE / MS or ME / MTech / MS in an Electronics / Electrical Engineering

Location                       : Bangalore

Mandatory Skills required:

·         Proven experience in the DFT area with both scan and mbist experience

·         On the scan front, experience should include scan insertion and verification (include ModelSim or VCS simulator) preferably with Synopsys DFTC and TetraMax or Encounter Test experience.

·         On the MBIST front, experience in memory BIST insertion and verification (include ModelSim or VCS simulator).

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RTL Design

Experience Level               : 2 – 8 yrs
Education                      : BE / MS or ME / MTech / MS in an Electronics / Electrical Engineering

Location                       : Bangalore

Role: The Engineer will be part of an ASIC design team responsible for digital logic design of next generation and legacy products. The candidate will participate in modeling, RTL implementation, conversions and verification. The candidate should be familiar with C, C++ and Verilog and/or VHDL. Must be able to work with minimal supervision and engage in technical dialogue.

Mandatory Skills required:

·         Experience with standard cell ASIC and / FPGA design.

·         Candidate should be familiar with RTL and gate level design and verification using VHDL and/or Verilog hardware description languages.

·         Basic understanding of CMOS ASIC fundamentals

·         Knowledge of all phases of ASIC design methodology

·         Module Level Designs - Micro Architecture, Design, Verification

·         SoC Integration

·         SDC, Timing Analysis

·         Verilog / VHDL

·         Linux/Unix environment

·         Team Player

·         Good Communication Skills

Desired Capabilities

·         Knowledge of Bus Protocols like AXI, AHB, SPI, USB, and Ethernet Protocol

·         Familiar with ARM microprocessors

·         Knowledge of System Verilog

·         FPGA based designs

·         Test Planning & Verification

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 Synthesis/STA

Experience Level          : 3 – 8 yrs
Education                    : BE / MS or ME / MTech / MS in an Electronics / Electrical Engineering

Location                       : Bangalore

Mandatory Skills required:

·         Worked on 45nm

·         Experience on Synthesis

·         Experience on STA

·         Should have worked on Synthesis using RTL complier

·         Should have worked on STA using Gold Time

·         Should be good at Flow and methodology.

·         Knowledge of TCL is an added advantage

·         Networking domain Knowledge is an added advantage

·         Working knowledge  of DDR is an added advantage

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Layout Engineers

Experience                   : 2-5 years

Education                    : BE / MS or ME / MTech / MS in an Electronics / Electrical Engineering

Location                       : Bangalore

Mandatory Skills required:

·         Mid level user to an expert user of Cadence Virtuoso-L/XL layout tool

·         Should have handled doing the verification checks, DRC/LVS/SRC/ANT/DFX for the laid out circuits.

·         Debug and understand the layout issues with corresponding schematics, Working largely from schematics, the candidate needs to be able to work with circuit design engineers to complete the layout of mixed signal circuits and top level connectivity.

·         should have worked in team environment and on Unix or Linux platforms.

·         Experience of working  at full-chip layout up to mask shop will be an added advantage.

·         Any further knowledge on writing scripts (skill/Perl/C/python) will be a plus

·         Adept in technicalities of drawing layout of very high-speed analog and digital circuits (high speed serial IO’s, analog circuits like op-amps, PLL/DLL, VREG’s, mixers etc) at deep submicron designs

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Memory Layout

Experience                   : 2-5 years

Education                    : BE / MS or ME / MTech / MS in an Electronics / Electrical Engineering

Location                       : Bangalore

Mandatory Skills required:

·         Experience in Layout development

·         Experience in DRC, LVS

·         Experience in OPUS-Cadence tools

·         Experience in Memory leafcell development

·         Expertise Needed

·         Electronics background

·         Unix knowhow

·         Basic Software knowhow, java and tcl basics will be an added advantage

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Analog Layout Designer

Experience                   : 2- 5 years

Education                    : BE / MS or ME / MTech / MS in an Electronics / Electrical Engineering

Location                       : Bangalore

Mandatory Skills required:

·         Experience in analog layout designs of trans receivers / adc / dac /IOs / LDO / PLL etc.

·         Proficient in Cadence Virtuoso, Calibre DRC / LVS, Deep submircron issues,

·         Good to have, Exposure to layout rules of 40 nm /  32 nm / 28nm

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Std Cell Characterization & Packaging

Experience                   : 2- 5 years

Education                : BE / MS or ME / MTech / MS in an Electronics / Electrical Engineering

Location                          : Bangalore

Mandatory Skills required:

·         FE Modeling Characterization & CAD views generation for various flow support (Cadence , Synopsys, etc)

·         Good understanding of  CMOS process & Transistor Level Concepts .

·         Good basic understanding of  digital fundamental Eldo

Good to Have

Basic understanding of  digital fundamentals