Hi All,
Please find below the description of the current job openings. We would look forward for more people like “U” to be a part of SmartPlay!!
If the referred candidate(s) join in two weeks time from 21 Sep 10, HOT JOB Bonus would be awarded else Standard Bonus would be awarded
We are planning to have weekend drives at Hyderabad and Chennai. If you have your referrals at these locations, please indicate so. We shall plan to meet them there itself
Design Verification
Ø Should have worked on SOC level verification on at least one project with constrained random methodology (eRM / VMM / OVM). Proficiency in one or more HVL's - System Verilog, C++, Vera, e, System C, Test Builder - is a must.
Ø Strong domain knowledge on one or more of PCIe, USB, Ethernet, ARM, AHB / AXI, AMBA, PHY Layer is a must
Ø Must be expert in building a verification environment with any of the above methodology, writing and debugging test cases.
Ø Should be able to enhance the Verification Coverage, Code coverage & Functional Coverage.
Ø Working knowledge of any one scripting language like Perl, Python, Unix Make, Unix Shell Scripts etc. is a must
Ø Experience level : 3 to 14 years
Ø Location : Bangalore, Hyderabad & Noida
Physical Design Ø Expertise in implementation TOP LEVEL / COMPLEX BLOCK LEVEL of multimillion gate SoC designs
Ø Technology: 45nm / 65nm / 90nm Technologies
Ø Design Complexity: Greater than 1Mn and up to 40Mn Gates
Ø Tools / Flows: Expertise in ICC Tools is a must, Scripting using TCL / Perl Desirable
Ø Skills: Should have very good conceptual understanding of the technology, design flow and implementation. Should have worked on all aspects of physical design including synthesis, floor planning, place and route, Clock Tree Synthesis, Clock Distribution, IP integration, extraction, Timing closure, Power and Signal Integrity Analysis, Physical Verification, DFM and Tape Out. Should be able to interface with Front End Design team to resolve Design Issues
Ø Experience level : 3 – 6 years
Ø Location Bangalore & Hyderabad
Ø Education : BE, BS, MS, ME – Electronics, Computer Science
Synthesis + STA ( Job Code: Ref: SYN+STA HJ 09202010 ) Ø Developing / running full chip level synthesis flow
Ø Proactive interaction with RTL designers to resolve warnings / errors reported during synthesis
Ø Performing static timing analysis on DC synthesized netlist
Ø Hands on experience with Design Compiler
Ø Expert in writing Perl/TCL scripts
Ø Ability to experiment with synthesis flows for area reduction and better timing closure
Ø Ability to understand and analyze RTL written in Verilog/VHDL
Ø Good documentation skills
Ø Good to have - RTL Coding experience
Ø Must be a results-oriented, problem-solver who requires minimal supervision and proven ability to work effectively in a fast-paced environment.
Ø Experience level : 4 to 8 years
Ø Location : Bangalore & Hyderabad
Ø Education : BE, BS, MS, ME – Electronics, Computer Science
Good to have
§ Spyglass Linting, CDC
§ Generating Spyglass Lint and CDC reports for full chip RTL
§ Running Cadence LEC on full chip RTL and working to resolve mismatches
§ Hands on experience with Spyglass and Cadence LEC
§ Expertise in Spyglass Lint/CDC checks and waiver creation
§ Ability to understand and analyze RTL written in Verilog/VHDL
§ Previous experience with synthesis and formal verification, hands on with Cadence LEC
§ Working knowledge of synthesis is a plus
§ Expertise in Perl is a plus
RTL Design ( Job Code: Ref: Design HJ 09202010 ) Ø Strong Logic Design Skills
Ø Must have experience in architectural and micro architecture
Ø Must have worked on coding of RTL blocks
Ø Unit level verification to meet various quality guidelines
Ø Knowledge on ARM architecture and bus structure
Ø Ability to understand design, make RTL changes in a sub system independently
Ø Ability to run simulations, and debug and fix bugs
Ø Familiarity with Spyglass lint/CDC tools is a big plus
Ø Should have experience working on at least one SOC (with on-chip processor)
Ø Hands on experience with independently designing complex modules.
Ø Must have experience in understanding the requirement & come up with a design
Ø Domain: Networking (TCP/IP, L2/L3 switch) with Processor: ARM Core - ARM 9 / ARM 11 and Protocols: AMBA,AXI,AHB
Ø Languages: HDLs – Verilog / VHDL
Ø Experience level : 4 to 12 years
Ø Location : Bangalore & Hyderabad
Ø Education : BE, BS, MS, ME – Electronics / Computer Science
Post Silicon Validation ( Job Code: Ref: PSV - HJ 09202010 )
Ø Should be strong in C / C++, Assembly programming,
Ø Proficient in embedded software development
Ø Should have good hands-on experience with lab equipments such as oscilloscopes, logic analyzers, embedded firmware debugging tools, etc used in resolving embedded firmware issues
Ø Should be able to develop validation scripts/drivers for the validation of hardware modules in the SOC. Create validation specifications, Run the SOC validation tests, Capture the observations and generate validation test reports, Identify the bugs in silicon, analyze, provide solutions/workarounds, track them to closure, Prototype/Emulate the SOCs/IPs and perform validation and software development
Ø Should Support software development teams by providing programming sequences, take electrical parameter measurements and do performance validation.
Ø Must be proficient in peripherals/interfaces such as: USB, SDIO, I2C, I2S, oneNAND, SDR, DDR, eMMC and writing code to exercise hardware functionality at an application level.
Ø Experience / Expertise with ARM Architecture and ARM assembly language.
Ø Experience / Expertise with ASIC FPGA prototyping tools is a plus.
Ø Must be a results-oriented, problem-solver who requires minimal supervision and proven ability to work effectively in a fast-paced environment.
Ø Experience level : 4 to 10 years
Ø Location : Bangalore
Ø Education : BE, BS, MS, ME – Electronics, Computer Science
You can send your profiles to pradeep_sto@yahoo.com (Giving my personal ID to avoid spam mails to my cmp ID)
