TCS IS HIRING - Science Graduates from 2011

AVA PROFILES FOR HIRING EVENT IN HYDERABAD ON 30th July'11 - GSD

                                                                       KINDLY REFER JAVA PROFILES FOR HIRING EVENT IN HYDERABAD ON 30th July'11 

Software Engineer- Java Reference Guide > Software Engineer - Java Pipeline Req. No. - 320691 Location - Hyderabad Job Responsibilities: Anticipate customer needs and proactively develops solutions to meet them Perform complex conceptual analyses and develop innovative solutions Analyze and interpret complex business requirements/ workflows and determine system needs Document detailed system specifications for large/ complex system maintenance and development requests Provide explanations and information to others on complex issues Demonstrate subject matter expertise in his/her chosen functional/ application area Analyze alternatives and recommendations Generate innovative ideas to resolve application problems The desired Skill set will be following: Total experience of 1.5 – 2.9 years Hands on with Core Java/ J2ee (Servlets/JSP/Struts/Spring) Hands on with any of the IDE ( Eclipse/RAD etc) Hands on with Oracle (9i/10g) with SQL queries and PL/SQL experience Good to have basic Unix Knowledge and knowledge of batch processes with Proc* would be a PLUS Willing to work in shifts and possess excellent written and verbal communication skills Click here to submit | Back top   *It is mandatory to submit your referrals online for referral bonus.   Click here to submit

Opening in Thomson Reuters - Hyderabad - DotNet professionals

 There is an opening in Thomson Reuters,Hyderabad  for DotNet professionals (Software Engineer/Senior Software Engineer).
 
The required skills are
 
1.) .Net, asp.net,c#,sql server , ssrs & ssis
 
2) Experience level : 3 - 6 years
 

 
Note: No mail ID provided...

Refferal Program - TCS

Simple Steps to Refer your buddy - To Refer your buddy (create EPIR number) 

Step 1: Create buddy's profile   
Go to Ultimatix --> WorkForce Management --> Global Recruitment System --> Referrer Home --> Create Buddy Profile. 

Step 2: Ask buddy to confirm profile 
Your buddy needs to log on to http://www.careers.tcs.com (using the EPIR number and password mailed to your buddy) and confirm the profile. 

Step 3: Ask buddy to upload resume 
Post confirmation of profile, your buddy needs to upload the application form and resume. 

To Know more about BYB 
Log on to  UItimatix > Global HR > Bring your Buddy > India Buddy Scheme 

To Refer your buddy (create EPIR number) 

* As per the scheme, BYB reward is applicable for 3 and above years of relevant experience. 
*All candidates registered in our Careers portal /GRS online will have a fast track process at the drive location. 
*The candidate should have the EPIR number at the time of interview. 
*EPIR number is mandatory to be eligible for the reward 

Recruitment drive is at Hyderabad - Design Verification and Physical Design

Hi Team,

Our next recruitment drive is at Hyderabad on 23 Jul 11 focused on Design Verification and Physical Design Domains.

Please do refer your friends / buddies / acquaintances who would suit the requirements to these positions and be a part of building our VLSI Team. The details of the current requirements are provided below.

Please send in your referral profiles to pradeep.sakhamoori@smartplayin.com with subject field of respective Job Code & Candidate Name. For Ex. PD-230711- Kirk Douglas

You would be eligible for referral bonus per policy. Should your referred candidate start at SmartPlay as an employee 08 Aug 11, you would be eligible for Hot Job Bonus. All others will be considered as referrals and Standard Referral Bonus.

Please mail all your referrals to pradeep.sakhamoori@smartplayin.com  latest by 21 Jul 11

1. Verification: (Job ID: DV1 - 230711)

a. Working Experience: 6 to 8 yrs

b. Technical skills (Should Have)

• Hands On Experience in RTL coding of digital designs in Verilog / VHDL and Verification of the designs done.
• Should be Strong in HDL’s (Verilog / VHDL), Digital Design, Micro Architecture, RTL coding, Design documentation.
• Should be Strong in Functional verification of designs viz. RTL Verification, Gate Level Verification, Emulation.
• Should have experience in designing / developing automated self checking test bench
• Strong Knowledge in HVL’s viz. Open Vera, System Verilog etc required
• Strong scripting skills in Scripting languages viz. TCL / PERL / csh etc.

c. Technical Skills (Desirable)

• Exposure to advanced verification methodologies like RVM, AVM or OVM etc.
• Exposure to ARM / MIPS firmware / assembly coding
• Domain knowledge in networking (IEEE 802.3) will be given preference.

2. Verification: (Job ID: DV2 - 230711)

a. Working Experience: 4 to 8 yrs

b. Technical skills (Should Have)

·         Strong Expertise in Functional Verification and Development of Test Plan / Test Cases for Functional Verification

·         Good experience in Debugging Simulation Results, enhancing Code Coverage & Functional coverage.

·         Should be Strong in Verilog / System Verilog / System C, C / C++

• Strong scripting skills in Scripting languages viz. TCL / PERL / csh etc.

c. Responsibilities

·         Performance Verification, Functional verification, Test case development, Running regressions & Debugging Failures

3. Verification: (Job ID: DV3 - 230711)

a. Working Experience: 3 to 5 yrs

b. Technical skills (Should Have)

·         Strong Domain Knowledge in OVM / Low Power Verification

·         Should be Strong in System Verilog / Verilog / VHDL

• Strong scripting skills in Scripting languages viz. TCL / PERL / csh
• Good at writing makefile scrips,
• Good at C, mySQL, database design

c. Technical Skills (Desirable)

·         Good to have ASIC Design Verification Project Experience in Verifying IP’s, SOCs

·         Knowledge in creation of test benches / verification environments, writing test plans etc.

4. Physical Design: (Job ID: PD-230711)

a. Working Experience: 2 to 10 yrs

b. Technical skills (Should Have)

·         Strong Physical Implementation expertise of multimillion gate SoC designs in cutting edge process technologies viz. 28 / 45 / 65nm

·         Should have working knowledge on all aspects of physical design including synthesis, floor planning, place & route, clock distribution, IP integration, extraction, timing closure, power & signal integrity analysis, physical verification, DFM, & Tape out

·         Should have very good understanding and command over all aspects of physical design

·         Should have strong expertise in atleast one of the Physical Design Tools viz. Synopsys IC Compiler / Magma Talus / Cadence SoC Encounter

• Strong scripting skills in Scripting languages viz. SKILL / TCL / PERL