Hi Team,
Our next recruitment drive is at Hyderabad on 23 Jul 11 focused on Design Verification and Physical Design Domains.
Please do refer your friends / buddies / acquaintances who would suit the requirements to these positions and be a part of building our VLSI Team. The details of the current requirements are provided below.
Please send in your referral profiles to pradeep.sakhamoori@smartplayin.com with subject field of respective Job Code & Candidate Name. For Ex. PD-230711- Kirk Douglas
You would be eligible for referral bonus per policy. Should your referred candidate start at SmartPlay as an employee 08 Aug 11, you would be eligible for Hot Job Bonus. All others will be considered as referrals and Standard Referral Bonus.
Please mail all your referrals to pradeep.sakhamoori@smartplayin.com latest by 21 Jul 11
1. Verification: (Job ID: DV1 - 230711)
a. Working Experience: 6 to 8 yrs
b. Technical skills (Should Have)
- Hands On Experience in RTL coding of digital designs in Verilog / VHDL and Verification of the designs done.
- Should be Strong in HDL’s (Verilog / VHDL), Digital Design, Micro Architecture, RTL coding, Design documentation.
- Should be Strong in Functional verification of designs viz. RTL Verification, Gate Level Verification, Emulation.
- Should have experience in designing / developing automated self checking test bench
- Strong Knowledge in HVL’s viz. Open Vera, System Verilog etc required
- Strong scripting skills in Scripting languages viz. TCL / PERL / csh etc.
c. Technical Skills (Desirable)
- Exposure to advanced verification methodologies like RVM, AVM or OVM etc.
- Exposure to ARM / MIPS firmware / assembly coding
- Domain knowledge in networking (IEEE 802.3) will be given preference.
2. Verification: (Job ID: DV2 - 230711)
a. Working Experience: 4 to 8 yrs
b. Technical skills (Should Have)
· Strong Expertise in Functional Verification and Development of Test Plan / Test Cases for Functional Verification
· Good experience in Debugging Simulation Results, enhancing Code Coverage & Functional coverage.
· Should be Strong in Verilog / System Verilog / System C, C / C++
- Strong scripting skills in Scripting languages viz. TCL / PERL / csh etc.
c. Responsibilities
· Performance Verification, Functional verification, Test case development, Running regressions & Debugging Failures
3. Verification: (Job ID: DV3 - 230711)
a. Working Experience: 3 to 5 yrs
b. Technical skills (Should Have)
· Strong Domain Knowledge in OVM / Low Power Verification
· Should be Strong in System Verilog / Verilog / VHDL
- Strong scripting skills in Scripting languages viz. TCL / PERL / csh
- Good at writing makefile scrips,
- Good at C, mySQL, database design
c. Technical Skills (Desirable)
· Good to have ASIC Design Verification Project Experience in Verifying IP’s, SOCs
· Knowledge in creation of test benches / verification environments, writing test plans etc.
4. Physical Design: (Job ID: PD-230711)
a. Working Experience: 2 to 10 yrs
b. Technical skills (Should Have)
· Strong Physical Implementation expertise of multimillion gate SoC designs in cutting edge process technologies viz. 28 / 45 / 65nm
· Should have working knowledge on all aspects of physical design including synthesis, floor planning, place & route, clock distribution, IP integration, extraction, timing closure, power & signal integrity analysis, physical verification, DFM, & Tape out
· Should have very good understanding and command over all aspects of physical design
· Should have strong expertise in atleast one of the Physical Design Tools viz. Synopsys IC Compiler / Magma Talus / Cadence SoC Encounter
- Strong scripting skills in Scripting languages viz. SKILL / TCL / PERL
